When it finishes successfully, it signals equivalent set, to suit certain problem specifications. If it fails due to some conditions, it These schemas may be specific to a particular application, signals an error, and backtracking is done to the task that had or may deal with general design techniques.
The designer process is rule- Function semantics, which describe the behavior associ- based. This The knowledge elements algorithm, to guide the selection of specific components. Each operator consists of a set of applicability conditions and a set of C. Knowledge about Available Components actions. The actions are mainly 1 subfunctions to be generated This module of knowledge specifies which components can or deleted, 2 information about control and data flow among be used to achieve a particular function, and how.
For example, the subgoals, and 3 initiation of subtasks procedural or rule- an AD-converter can be operated in several modes: polling, based. These knowledge bases are briefly discussed below: interrupt, using wait-signal, etc. Knowledge about the Application World selection. Again, each mode may be realisable by different This component of the knowledge base describes what the chips, each having its own interface requirements.
For programmable chips e. Component descriptions, which contain the details of the IV. These systems, which include over-current protector [, over- details are used to design the interface circuitry between current protector with interrupt [12], speed controller for a dc different components. In the previous section, Interfacing operators, which are a collection of schemas we have shown the intermediate results for the design of a specifying how two components have to be interfaced.
In this section, we show the results for [l 11, This includes schemas for instantiating ports, inserting and for its variation [12]. These schemas are divided based over-current protection system [l 13, where the current into two categories: digital interfacing operators and limit is predefined A and hardcoded in the system.
Also, analog interfacing operators. The fault current may go up to A. After the user-interaction phase, the problem specifications are as shown below: D. The Transformation Operator for sensing the speed of a DEX applies the different knowledge sources-knowledge motor is shown below; its statechart representation is shown about the application world and knowledge about the ap- in Fig. It has a set of activation conditions, and a set plication-to decompose the goal at different levels of task of actions that are performed when the conditions are true.
Available ;; subsequently ADC-chips did not have enough precision to accomodate the fn counter wait compute1 portV? AD IO 0 - 1. Allocation output for over-current protector. Algorithm generated for over-current protector. Program for over-current-protector. The interface designer prepares the device interfaces, enables the RST5.
Hardware configuration for over-current protector. The resultant software consists of a main program and the service routine for RST5. In the main program the interrupt is enabled, and and a successive-approximation function are also allocated. Similar allocation has been done for the two current-transformers.
Next, the interface to V. The We have presented a methodology for automating the design configuration of the resultant circuit is shown in Fig. First, an integrated approach linear order, and the software generated for it is shown in to the design of hardware and associated software has been Fig. Thus software is not optimal on several counts: 1 developed. Second, a knowledge-based, domain-independent all the initializations of the can be clubbed together, methodology for designing microprocessor-based application and shifted to the initial part of the program; and 2 instead systems has been developed.
The techniques developed are of implementing successive-approximation by a subroutine, independent of both the application domain and the component a macro would have yielded a faster response. However, domain. These techniques would greatly benefit the devel- these optimizations may be done easily by existing compiler opment of such systems, which have widespread industrial technology. The use of the powerful statechart formalism [8] As another example, we design a system for the problem to specify design problems makes DEX capable of designing specification shown in Fig.
The examples shown in this only when a failure occurs. The algorithm designer adds the paper, from different domains, demonstrate its efficacy and states and devices for sensing the current ADC and CT , generality. The architecture designer As an extension of the design work, we also generate the allocates the Comparator-event to the RST5. This design plan would be used Raj S. Mitra received the B. He is working toward the Ph. From to , he was with C. Rich and K. New York: McGraw- Hill, Gero, Knowledge Engineering in Computer-aided Design.
New York: North Holland, , also in Proc. Mitchell, L. Steinberg, and J. Pattern Anal. His research interests tion plus what? IEEE Syst. Sofiware Eng. Chou, R.
Ortega, and G. Aided Design, , pp. Druinsky and D. Berry and G. He received the Ph. Al-Nema, S. Bashi, and A. Department of Electronics and Electrical Commu- A. Aho, R. Sethi, and J.
Currently, niques and Tools. Reading, MA: Addison-Wesley, New York: gineering there. Pal, Microprocessors: Principles and Applications. New Delhi, Open navigation menu. Close suggestions Search Search. User Settings. Skip carousel. Carousel Previous. Carousel Next. What is Scribd? Explore Ebooks. Bestsellers Editors' Picks All Ebooks. Explore Audiobooks. Bestsellers Editors' Picks All audiobooks. Explore Magazines.
EMC design in a microprocessor based system Aditya Emy. A short summary of this paper. Download Download PDF. Translate PDF. Like a high for the design of printed rise building or any kind of circuit using the high speed building, if the first brick microprocessors. The paper also is not right, the building includes some EM1 measurement won't stand. Similarly, cor- results of the microprocessor rect PCB design would have based system.
The table. The design of a heart and soul of the micro- microprocessor based system processor[1,2]. Multilayer board Track lines to the opti- boards are recommended f o r use mum placements of microproces- where in the power supply and sor in the PCB and proper pin return, and Zero-signal refer- filtering of the power and ence are all realized typical- signal lines.
The present ly on separate one ounce microprocessor based system copper foil planes. It is inter-connect lines, correct important to note that the placement of microprocessor upper and lower faces of subsystem etc.
An Inter connect ground return level B is lines acts as antenna radiating electrically isolated by about and receiving noise when its 50db.
Conflicts description schemas to know the functionality of the compo- are marked for hardware implementation. For example, in the nents and component compatibility information. The latter is parallel path shown in Fig. In such cases, this algorithm The Counter and Wait of Fig. Finally, constraints-they may be merged and implemented by soft- the third subtask heuristically allocates addresses to each ware, but a hardware timer, if available, is preferred for the component.
The component allocation and address allocation tables for the speed-controlled are summarized in Fig. The devices C. Architecture Design listed there are assumed to be available in the device library.
Interface Design ponent Allocation and Address Allocation Tables, indicating A substantial part of the design of microprocessor-based the configuration of hardware components in the system. This systems is the design of device interfaces. In our approach, task consists of three subtasks.
To along with their number, and the constraints imposed on them. Allocation output for speed-controller. These schemas use information 19 Attach program heders: data declarations and include-files from the component and address allocation tables.
In addition, Fig. Algorithm for software generation. For example, the p f ' s by C-language templates, available in the Programming precision of a data may be restricted by the data bits supplied Schemas knowledge-base. After the initial program is gener- by a component, and this precision constraint has to be used ated, a peep-hole optimization [ is done, to remove obvious to interpret the data properly.
This is the case, in the above redundancies in the code. The algorithm for generating the example, where the set-value of the speed is read from a 8- software is summarised in Fig. Since the allowable for the dc-motor example is shown in Fig. However, if the user had specified precision F. Circuit Design greater than 8 rpm, then an additional switch and port would This task performs the interfacing between the allocated have been added to the design.
This includes adding extra circuitry for address decoding, transforming mismatching signals, and connecting E. Software Design the pins of the components. This task is achieved by using the component description schemas and interfacing operators During the phase of algorithm design, some p f ' s of the available in the component knowledge-base. This part serves as are applied iteratively, till all the pins of the chips are the specification for software design.
The present task refines connected consistently, that is, without violating the interface these p f ' s further by: constraints with its neighbors. The extra components that have merging parallel paths into a single path, by resolving the been added in the example design are ALE, address decoder, partial order and performing live-dead analysis of data and free-wheeling diode.
After the actual C. These are removed by this task. To design tails of the target machine e. This process converts the statechart machines. Now, each of the above mentioned handled by the compilers. System architecture. This goto L l ; knowledge-base is modeled as a semantic network [14] of I objects and their relations.
Program for speed-controller of dc motor. Transformationoperators, which describe how a function may be achieved by a combination of other subfunctions, partial design, transform it, and store the new results in the or how a set of functions may be transformed into another same data structure. When it finishes successfully, it signals equivalent set, to suit certain problem specifications. If it fails due to some conditions, it These schemas may be specific to a particular application, signals an error, and backtracking is done to the task that had or may deal with general design techniques.
The designer process is rule- Function semantics, which describe the behavior associ- based. This The knowledge elements algorithm, to guide the selection of specific components. Each operator consists of a set of applicability conditions and a set of C. Knowledge about Available Components actions.
The actions are mainly 1 subfunctions to be generated This module of knowledge specifies which components can or deleted, 2 information about control and data flow among be used to achieve a particular function, and how. For example, the subgoals, and 3 initiation of subtasks procedural or rule- an AD-converter can be operated in several modes: polling, based. These knowledge bases are briefly discussed below: interrupt, using wait-signal, etc. Knowledge about the Application World selection.
Again, each mode may be realisable by different This component of the knowledge base describes what the chips, each having its own interface requirements.
For programmable chips e. Component descriptions, which contain the details of the IV. These systems, which include over-current protector [, over- details are used to design the interface circuitry between current protector with interrupt [12], speed controller for a dc different components.
In the previous section, Interfacing operators, which are a collection of schemas we have shown the intermediate results for the design of a specifying how two components have to be interfaced.
In this section, we show the results for [l 11, This includes schemas for instantiating ports, inserting and for its variation [12]. These schemas are divided based over-current protection system [l 13, where the current into two categories: digital interfacing operators and limit is predefined A and hardcoded in the system. Also, analog interfacing operators. The fault current may go up to A.
After the user-interaction phase, the problem specifications are as shown below: D. The Transformation Operator for sensing the speed of a DEX applies the different knowledge sources-knowledge motor is shown below; its statechart representation is shown about the application world and knowledge about the ap- in Fig. It has a set of activation conditions, and a set plication-to decompose the goal at different levels of task of actions that are performed when the conditions are true.
Available ;; subsequently ADC-chips did not have enough precision to accomodate the fn counter wait compute1 portV? Allocation output for over-current protector. Algorithm generated for over-current protector. Program for over-current-protector. C-fl 7seg-dec display we want level triggerring here , and the other states are x 4 FND x 4 allocated as in the previous example.
The interface designer prepares the device interfaces, enables the RST5. Hardware configuration for over-current protector.
The resultant software consists of a main program and the service routine for RST5.
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